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Enhanced local bus
7
Enhanced local bus
This section describes the DC and AC electrical specifications for the enhanced local bus interface of the
MPC8309.
7.1
Enhanced local bus DC electrical characteristics
The following table provides the DC electrical characteristics for the enhanced local bus interface.
Table 17. Enhanced local bus DC electrical characteristics
Parameter
High-level input voltage
Low-level input voltage
High-level output voltage, I OH = –100 μ A
Low-level output voltage, I OL = 100 μ A
Input current
Symbol
V IH
V IL
V OH
V OL
I IN
Min
2
–0.3
OV DD – 0.2
—
—
Max
OV DD + 0.3
0.8
—
0.2
±5
Unit
V
V
V
V
μ A
7.2
Enhanced local bus AC electrical specifications
The following table describes the general timing parameters of the enhanced local bus interface of
MPC8309.
Table 18. Enhanced local bus general timing parameters
Parameter
Local bus cycle time
Input setup to local bus clock (LCLK n )
Input hold from local bus clock (LCLK n )
Local bus clock (LCLK n ) to output valid
Local bus clock (LCLK n ) to output high impedance for LAD/LDP
LALE output fall to LAD output transition (LATCH hold time)
LALE output rise to LCLK negative edge
LALE output fall to LCLK negative edge
Symbol 1
t LBK
t LBIVKH
t LBIXKH
t LBKHOV
t LBKHOZ
t LBOTOT
t LALEHOV
t LALETOT
Min
15
7
1.0
—
—
3
—
–5.0
Max
—
—
—
3
4
—
3
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Note
2
3, 4
3, 4
3
5
—
—
—
Notes :
1. The symbols used for timing specifications follow the pattern of t (first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t (first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t LBIXKH1 symbolizes local bus
timing (LB) for the input (I) to go invalid (X) with respect to the time the t LBK clock reference (K) goes high (H), in this case for
clock one(1).
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from OV DD /2 of the rising/falling edge of LCLK0 to 0.4 × OV DD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 3
Freescale Semiconductor
19
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